Bootstrap driver circuits for an mos memory

Abstract

A bootstrap driver circuit is used asynchronously in a static RAM. A capacitor is coupled between second and third nodes, and a charge pump is coupled to provide charge to the second node. Address bits can be applied to the gates of respective transistors whose drains form a common node coupled to the source of a low impedance transistor whose drain is coupled to a first node. An inverter is coupled to the common node for applying a delayed input signal to the gates of first and second enhancement mode transistors. This provides a discharge path for the third node in response to a low level memory address signal thereby to maintain a differential voltage across the bootstrap capacitor. Also disclosed is an input protection circuit when the bootstrap driver is used as a chip select buffer. A timing circuit receives an input signal and develops a first signal and a delayed signal, both of which are applied to the bootstrap driver. One embodiment particularly useful for overcoming glitches on an input signal uses a charge pump, a latch and release network, an inverting buffer, and a bootstrap isolation transistor. An early discharge transistor and a late discharge transistor provide a discharge path for the isolation transistor. The early discharge transistor is responsively coupled to the digital input signal, and the late discharge transistor is responsively coupled to the output of the inverting buffer.