The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 1985
Filed:
Dec. 13, 1983
Junichi Nishizawa, Sendaishi, Miyagi, JP;
Soubei Suzuki, Miyagi, JP;
Takashige Tamamushi, Miyagi, JP;
Other;
Abstract
A method for forming a semiconductor photodetector array having a matrix of pixels, each constituted by a single SIT (Static Induction Transistor). A field oxide layer is formed on a first main surface of a silicon wafer. Portions of a field oxide layer are then removed from predetermined regions of the first main surface. In these predetermined regions are formed a control gate region and a shielding gate region, with the shielding gate region surrounding the control gate region. Oxide layers are formed on the control gate region and shielding gate region. Portions of the field oxide layer between the control gate region and shielding region are removed to partially expose the first main surface of the silicon wafer, and a first main electrode region is formed in the exposed portion. A first conductive electrode is then deposited on the first main region, whereupon the entirety of the first main surface of the silicon wafer is covered with a first insulating layer. Portions of the first insulating layer are then removed from the control gate region, and the entirety of the first main surface of the silicon wafer is covered with a second insulating layer. A second conductive electrode is then formed on the second insulating layer upon the control gate region. Portions of the first and second insulating layers and the oxide on the shielding gate region are removed to provide a contact hole. The first main surface of the silicon wafer is then covered with a metal layer, portions of which are subsequently removed from the control gate region. Finally, an electrode for the second main electrode region is deposited on the second main surface.