Logic state analyzer with sequential triggering and restart

Abstract

A logic state analyzer monitors an ongoing succession of logic states occurring in a collection of n-many digital signals, and stores in a memory a set of logic states selected from the ongoing succession. A logic state is any one of the 2.sup.n -1 possible patterns the n-many digital signals may exhibit. The memory is of some convenient fixed number of locations, and once the memory is filled the oldest stored logic states are overwritten as the newest logic states are stored. Various storage qualification criteria may be specified, in which case an individual logic state is not stored unless it meets those criteria. Upon recognition of a specified trigger condition in the succession of logic states the logic state analyzer stores an operator selectable number of additional logic states, after which the monitoring and storing of logic states ceases and the stored contents of the memory are displayed. The trigger condition may be the detection of a designated sequence of selected logic states. A sequence detector monitors the ongoing succession of logic states. To satisfy the sequence and thus meet the trigger condition the first logic state in the sequence must occur and be subsequently followed by the next logic state in the sequence, and so on, until all selected logic states in the designated sequence have occurred. It may also be required that each logic state in the sequence be detected a selected number of times before an occurrence of the next logic state in the sequence can contribute toward satisfaction of the sequence. A logic state may be designated as a restart state whose occurrence nullifies any partial satisfaction of the sequence and causes the process of sequence satisfaction to begin afresh.