The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 1984
Filed:
Jan. 07, 1983
Applicant:
Inventors:
Hon W Lam, Dallas, TX (US);
Ham-Tzong Yuan, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
148175 ; 29571 ; 2957 / ; 2957 / ; 2957 / ; 29578 ; 29580 ; 148-15 ; 148174 ; 148187 ; 156603 ; 156612 ; 156D / ; 156D / ; 427 531 ; 427 86 ; 427 35 ; 357 42 ; 357 49 ; 357 50 ; 357 59 ;
Abstract
A method of forming a semiconductor device having a single crystal silicon substrate, the surface of which includes exposed silicon areas bounded by and coplanar with insulating oxide regions. A polysilicon layer is deposited thereon and annealed to form a single crystal epitaxial region overlying the exposed substrate areas while the regions overlying the oxide areas in the substrate surface may be of polycrystalline form. This structure is applied to NMOS, CMOS, MESFET, and I.sup.2 L devices to achieve high packing density, high speed, improved isolation between devices and reduced susceptibility to latch-up.