The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 1984
Filed:
Feb. 19, 1982
Charles R Hoffman, Raleigh, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A non-volatile EAROS (Electrically Alterable Read Only Storage) memory array with fast reading and writing capability and a minimized cell size. Each cell of the array is composed of a floating gate first FET and a standard second FET connected in series between a reading bit line and a programming bit line for the row in which the cell is located. The floating gate of the first FET is connected through a capacitor to the common connection point between the first and second FET. DEIS (Dual Electron Injection Stack) material is used for the dielectric of a capacitor lying above the floating gate of the first FET. In programming the cell, a positive charge is stored on the floating gate of the first FET. When the cell is erased, the charge on the floating gate is reduced to zero, or at most a small negative charge. Because no large negative charge is stored on the floating gate, the voltages which can be applied to the diffusions of the cell are reduced, and thereby the cell area is correspondingly reduced.