The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 1984

Filed:

Aug. 04, 1982
Applicant:
Inventors:

Michael F Maas, White Bear Lake, MN (US);

Max S Hendrickson, Forest Lake, MN (US);

Assignee:

Honeywell Inc., Minneapolis, MN (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ; H04L / ; H03K / ;
U.S. Cl.
CPC ...
329 50 ; 307526 ; 328134 ; 329107 ; 329110 ; 375 88 ; 375 94 ;
Abstract

A frequency shift key demodulator produces an output data stream based upon whether a FSK modulated input signal has a frequency (f.sub.FSK) which is greater than or less than a reference frequency (f.sub.0) of a reference (REF) signal. The demodulator includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The demodulator also includes first and second sequence detectors, first and second integrating shift registers, and a decision circuit. The first sequence detector provides an output signal to the first shift register indicating that the FSK signal has a frequency less than the REF signal based upon detection of a first predetermined sequence of the code from the sequence generator. Similarly, the second sequence detector senses a second predetermined sequence of the code indicating that the FSK signal has a frequency greater than the REF signal and provides an output signal to the second shift register. At the end of a predetermined time period, the decision circuit compares the content of the first and second shift registers and produces an output bit of the data stream.


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