The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 1984

Filed:

Jul. 05, 1983
Applicant:
Inventor:

Eric D Neely, Phoenix, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307473 ; 307254 ; 307456 ;
Abstract

A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that has an enhanced transition from the active high to the active low. An output means includes a first transistor for supplying current to the output and a second transistor for sinking current from the output. A phase splitter means coupled to the output means determines the conductivity of the first and second transistors. An input means is responsive to an input signal and controls the phase splitter means. An output enable means is provided that disables both the first and second transistors for providing the high impedance output. A feedback means for enhancing the downward transition of the output signal from an active high to an active low includes a feedback transistor having a base connected to a supply voltage terminal by a resistor which can be used to vary the speed of the downward transition. A diode is coupled between the collector of the feedback transistor and the output terminal. The feedback transistor is reverse biased, except when the output signal is transitioning from the active high to the active low. A second diode is coupled between the base of the first output transistor and the collector of the feedback transistor for discharging stored base-collector capacitance of the first output transistor.


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