The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 1984
Filed:
Jan. 19, 1982
Applicant:
Inventors:
Yiu-Fai Chan, Saratoga, CA (US);
Allen L Evans, Colorado Springs, CO (US);
Assignee:
Intersil, Inc., Cupertino, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307264 ; 3072 / ; 307279 ;
Abstract
A CMOS digital level shifter circuit is provided which latches one transistor of a complementary transistor pair off when the other transistor of the pair is on to prevent direct current dissipation of power when the input signals to the shifter circuit are not in transition.
Chan, Yiu-Fai. (1984). Monolithic cmos low power digital level shifter (U.S. Patent No. 4486670). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4486670
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile