Signal processor device with conditional interrupt module and

Abstract

Signal processor device having a processor module and a conditional interrupt module for use in a multiprocessor system employing these signal processor devices. The processor module has address, data and control inputs and outputs, including an interrupt signal input for receiving an incoming interrupt request signal. The signal processor device has at least one conditional interrupt module in which the identity address of the signal processor is present, said interrupt module having inputs for receiving an incoming external interrupt request signal with corresponding destination address. The conditional interrupt module also has comparators in which its identity address is compared with the destination address. If the addresses agree, an interrupt signal is fed to the interrupt signal input of the processor module. The processor module may also have an interrupt signal output and be provided with an arbitration module to prevent conflicts between several interrupt requests. The provision of the conditional interrupt module enables interrupts to be processed in a multiprocessor system employing a plurality of such devices without all the devices being initially interrupted and without it being necessary to provide a multiplicity of interrupt lines.