The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 1984
Filed:
Apr. 08, 1982
Shuzo Tsugane, Tokyo, JP;
Nippon Electric Co., Ltd., Tokyo, JP;
Abstract
There is provided a code converting circuit for converting digital signals of fixed length codes into variable length codes and delivering a train of variable length codes produced by the conversion parallelly every predetermined K bits. The converting circuit comprises: a variable length code converter for converting an input fixed length code into a variable length code, sending the variable length code to an output signal line of K bits starting from a bit position next to that indicated by the output value of a first flip-flop, and sending an overflowing portion of the variable length code to an overlfow signal line; an adder with a modulo of K for adding the bit number of the variable length code corresponding to the input fixed length code to the output value of the first flip-flop; an OR circuit for receiving the output from the output signal line of the variable length code converter and the output from a second flip-flop; a switching circuit receiving the output signal of said OR circuit and the overflow signal from said variable length code converter and being responsive to a carry signal of the adder to selectively deliver as an output thereof one of the input signals; and a third flip-flop for storing the output signal of said OR circuit and delivering the stored value during the rise of the time slot following the delivery of the carry signal of the adder. The first flip-flop functions to delay the output value of the adder by one time slot and delivers the delayed output to the variable length code converter and the adder. The second flip-flop functions to delay the output signal of the switching circuit by one time slot and delivers the delayed output signal to the OR circuit.