The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 1984
Filed:
Jul. 14, 1982
Yasuhiko Fujii, Yamato, JP;
Victor Company of Japan, Limited, Yokohama, JP;
Abstract
Each block of data having information data and redundant bits is transmitted without any synchronous signal bit word, while transmitted data is processed to find the boundary between consecutive data blocks so that a synchronous signal will be produced at the receiving end. The system for producing the synchronous signal comprises a cyclic redundancy check (CRC) circuit, a frequency divider for dividing the frequency of shift clock pulses and a reset pulse generating circuit. The reset pulse generating circuit is responsive to the output signal from the frequency divider and the shift clock pulses to produce periodically first and second reset pulses with which the CRC circuit and the frequency divider are initialized. The reset pulse generating circuit is further responsive to an error signal from the CRC circuit so that further first and second reset pulses are produced with which the CRC circuit and the frequency divider are initialized again. Initialization is repeated until the frequency divider is synchronous with the bits of the data blocks, and once synchronizm is established, the output signal from the frequency divider can be regarded as the synchronous signal indicative of the boundary between any two consecutive data blocks.