Digital data apparatus having a plurality of selectively addressable

Abstract

Digital data apparatus comprising a processing unit which can have access to different numbers of memory units over a common data bus. The processing unit can address the memory units with select signals over individual leads of an address bus. Address codes containing select signals are valid when they select only a single memory unit. The validity of an address code is determined in the processing unit by comparing it with a corresponding identification code read over the data bus from a memory unit addressed by the code. Because an address code containing more than one select signal may select more than one memory unit, each address code has associated with it a number of flag bits which signify how many select signals the address code contains, and the corresponding identification code includes these flag bits. When an address code selects more than one memory unit there will be conflict on the data bus between the address code protions of the read identification codes. However, the flag bit portions of these read identification codes are not in conflict and can be compared with the flag bits associated with the address code being used to determine whether or not this address code is valid.