Logic state analyzer with graph of captured trace

Abstract

A logic state analyzer monitors an ongoing succession of states occurring in a collection of digital signals, and stores in a memory a set of states selected from the ongoing succession. The memory is of some convenient fixed number of locations, and once the memory is filled the oldest stored states are overwritten as the newest states are stored. Various storage qualification criteria may be specified, in which case an individual state is not stored unless the state meets those criteria. Upon recognition of a specified trigger condition in the succession of states the logic state analyzer stores an operator selectable number of additional states. The trigger condition may be as simple as the occurrence of a single specified state or may be as complex as the satisfaction of a sequence of specified states. The resulting collectivity of states stored in the memory may be termed a captured trace. Each of the states in the captured trace is a pattern of logical values for the individual digital signals in the collection thereof. That is, each state is also a bit pattern, and is expressable as a magnitude in a selected radix such as binary, octal, or hexadecimal. The states of the captured trace also possess the natural chronological order in which they were stored into the memory. The captured trace is presented as a graph in cartesian coordinates. The graph is a series of points, each representing a state in the captured trace. The ordinate of each point is the magnitude of the state rendered in a selected radix. The abscissa of each point is the ordinal number indicative of the state's chronological position in the captured trace.