The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 1984
Filed:
Mar. 31, 1982
Applicant:
Inventor:
Hirofumi Takeda, Yokohama, JP;
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307455 ; 307443 ; 307475 ; 3072 / ;
Abstract
An emitter-coupled logic circuit device comprises first and second voltage supply lines connected, respectively, to ground and an external voltage source, a third voltage supply line, having a potential between that of the first and second voltage supply lines, an output buffer circuit connected between the first and third voltage supply lines, and an inner gate circuit connected between the third and second voltage supply lines. The current flowing through the output buffer circuit also flows through said inner gate circuit.
Quick Actions:
Takeda, Hirofumi. (1984). Emitter-coupled logic circuit device (U.S. Patent No. 4477740). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4477740
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile