The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 1984
Filed:
Dec. 04, 1981
Applicant:
Inventor:
Kiyoshi Miyasaka, Yokohama, JP;
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; G11C / ;
U.S. Cl.
CPC ...
365205 ; 357 23 ; 357 41 ; 357 45 ; 365149 ; 365208 ;
Abstract
The present invention discloses a memory cell layout of a dynamic RAM of a folded bit line type MOS FET wherein the bit line pairs are extended in parallel away from the sense amplifiers. The present invention includes a particular bit line pair and at least one bit line of an adjacent bit line pairs positioned between the particular bit line pair and makes the capacitor regions corresponding to the mutually adjacent bit lines interleave and thereby improves the area efficiency of the capacitor region.
Miyasaka, Kiyoshi. (1984). Dram with interleaved folded bit lines (U.S. Patent No. 4476547). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4476547
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