Symbol synchronizer for mpsk signals

Abstract

A symbol synchronizer, as for use with apparatus for detecting MPSK signals to provide complex sampled data descriptive of keying signal phase, in which the timing of the resampling can be controlled with resolution that is a fraction of the time between successive complex data samples. The symbol synchronizer uses a first digital controlled oscillator to recover the MPSK baseband signal sampled at a frequency f.sub.i rate. The MPSK signal is operated on to recover a sampled data description of the envelope of the MPSK signal sampled at a frequency f.sub.s, which may equal f.sub.i or be down-sampled therefrom. This is digitally filtered to provide a sampled data locking signal to a second digital controlled oscillator, which uses modular arithmetic to generate a digital sampled data description at f.sub.s rate of a sawtooth waveform repetitive at f.sub.k keying rate. In this second digital-controlled oscillator an adder sums its output as delayed by a full f.sub.s clock cycle, the error signal, and a constant term. The output of this adder (ignoring the overflow, to implement the modular arithmetic) is the sawtooth waveform with f.sub.k fundamental frequency subsequently used in the symbol synchronizer. The sawtooth waveform in sampled data form is adapted for digital phase shifting by linearly combining it with a programmable phase correction signal in sampled data form. The shifted waveform is used as the carrier signal for resampling the MPSK signal to provide complex samples, phased locked to f.sub.k keying rate, for application to the circuitry for deciding the keying phase of the received MPSK signal.