The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 1984

Filed:

Sep. 28, 1982
Applicant:
Inventor:

Tadashi Kiriseko, Kanagawa, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
2957 / ; 2957 / ; 29578 ; 29580 ; 29591 ; 148175 ; 148187 ; 156643 ; 156653 ; 156657 ; 357 49 ; 357 50 ;
Abstract

In a process for producing a semiconductor device, having a thick silicon oxide layer, on an isolation region, an oxide layer is selectively formed on an area for providing the isolation region of the epitaxial layer. Then an anti-oxidation masking layer is selectively formed on the oxide layer. The semiconductor substrate is selectively oxidized using the anti-oxidation masking layer for forming the thick silicon oxide layer. The anti-oxidation masking layer on the silicon oxide layer, which corresponds to the area for providing the isolation region, is removed and impurities are introduced into the area for providing the isolation region. Then the semiconductor substrate is oxidized in an oxidizing atmosphere so that the impurities are activated to form an isolation region and an oxide layer on the isolation region, the oxide layer having an increased thickness. The thus-obtained thick silicon dioxide layer makes the parasitic capacitance between the conductive lines and the isolation region small.


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