The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 1984
Filed:
Dec. 16, 1981
Robert C Colineau, Angers, FR;
Abstract
The invention relates to apparatus for positioning and holding a screen carrier in a serigraphic machine. The positioning and holding apparatus is essentially constituted by two parallel grooves (21, 22) machined in the screen carrier (10) and cooperating stops and a side latch mechanism on the machine. The two grooves have at least one extremity opening on the same edge (C1) of the screen carrier. In these two grooves (21, 22) are respectively mounted the two stops (23, 24) which are designed to come respectively into contact with two fixed reference pins carried by the serigraphic machine. During insertion of the screen carrier, by sliding in its plane along two sides of the serigraphic machine, the two reference pins ride in the respective slots contacting the stops when the screen carrier is inserted fully. A latch locking arrangement is provided on the machine or maintaining and holding the screen carrier in position once the reference pins are in contact with the associated stops. Additional bores may be provided in the screen carrier on the axis of the grooves to cooperate with further reference pins and an articulated holding lever for assuring adjustment of the pattern of the screen with respect to the screen carrier before mounting of the screen carrier in the serigraphic machine. The invention applies notably to the manufacture of substrates of integrated circuits.