Power divider/combiner circuit as for use in a switching matrix

Abstract

A one port-to-M port passive signal power divider circuit (or combiner circuit) where M>2 and .noteq. 2.sup.N, M and N are integers, includes M - 1 two-way in-phase passive power dividers having a signal delay D through each path in one or more delay devices having delay D. Each output of each two-way power divider is coupled to an input of another power divider, a delay line or an output port, the arrangement being such that the delay through all ports of the power divider are equal. In accordance with a further embodiment of the invention the outputs of a passive power divider are connected to two-way switches using active components. The switches under control of a control circuit are utilized to switch the input signal to the power divider to any one of 2.multidot.M output terminals of the switches.