The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 1984

Filed:

Sep. 29, 1982
Applicant:
Inventors:

David A Wilson, Palo Alto, CA (US);

James L Buxton, Palo Alto, CA (US);

Philip S Green, Atherton, CA (US);

Donald J Burch, Los Altos, CA (US);

John F Holzemer, Menlo Park, CA (US);

S David Ramsey, Jr, Palo Alto, CA (US);

Assignee:

SRI International, Menlo Park, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N / ; G01N / ; G06G / ;
U.S. Cl.
CPC ...
128660 ; 364821 ; 73602 ; 73631 ;
Abstract

An ultrasonic imaging system (50) has an array (52) of transducer elements (54-1 through 54-21) for receiving ultrasonic signals reflected from within an inhomogeneous object (16) being examined. The system (50) has a means (80, 84, 88, 94) connected to generate an image in response to the ultrasonic signals. A cross-correlator (70) is connected to compare the signals received by the transducer elements (54-1 through 54-21). An output addressing circuit (130) is connected to inhibit or otherwise modify gain of selected ones of the signals based on the comparison to reduce multipath ultrasonic wave interference, refraction or obstruction image distortion or degradation. A preferred ultrasonic imaging array (52) for this purpose and for time delay image distortion correction has a plurality of segmented, annular transducer elements (54-2 through 54-21). The elements (54-2 through 54-21) are formed as sectors of circles with substantially equal arc lengths. A digital signal processing circuit for the system (50) has a plurality of dual port RAMs (66-1 through 66-21) as delay lines and a cross-correlator (70) including an output addressing circuit (130) controlled by a microcomputer (128). The output addressing circuit (130) generates addresses for output of information from the dual port RAM delay lines (66-1 through 66-21) to accomplish time delay correction and elimination or other gain modification of ultrasonic signals with multipath interference, refraction or obstruction.


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