The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 1984
Filed:
Mar. 15, 1982
Kevin Luke, Austin, TX (US);
Robert N Allgood, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
An input buffer circuit for translating TTL level inputs to CMOS levels and which constitutes a part of a monolithic semiconductor device is provided. An input inverter stage has the source of its load transistor connected via a bipolar transistor to a first voltage level. When a second voltage level at which the monolithic semiconductor device is intended to operate exceeds the first voltage level, an MOS transistor coupled in parallel with the bipolar transistor bypasses the bipolar transistor and connects the source of the load transistor directly to the first voltage level, thus eliminating the V.sub.BE drop of the bipolar transistor. The bypass means compensate for the body effect of the load transistor and maintain the switch point of the input inverter stage at a relatively constant point.