Data receivers incorporating error code detection and decoding

Abstract

A data receiver is required to detect successive 50-bit frames of data which are transmitted without any pause between frames and with a start bit value of 1 as the only start-of-frame indication. Error detection and correction is obtained by appending at the transmitter a 13-bit check word to 36 data bits (and the start bit), the value of the check word being chosen such that division of the error-free composite 49-bit code word by a predefined generator polynomial yields a syndrome (remainder) of zero. Calculation of a new syndrome value by the receiver at the speed necessary during initial frame synchronization (i.e. for each successive bit) is effected with an iterative procedure in which the previous syndrome value is left-shifted one place and the newly received digit is appended to it; the generator polynomial is added to the result by modulo-2 arithmetic if the most significant digit of the shifted syndrome word is a 1; and the remainder of -2.sup.49 divided modulo-2 by the generator polynomial is added to the result of the previous step by modulo-2 arithmetic if the digit received 49 bits before the newly received digit is a 1.