The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 1984
Filed:
Dec. 05, 1983
Christopher W Kapral, Belmont, CA (US);
GTE Network Systems Incorporated, Phoenix, AZ (US);
Abstract
An integratable PCM decoder that is relatively insensitive to parasitic and stray capacitance effects and that requires a total capacitance of only 32 times the normalized capacitance Co of the smallest capacitor thereof. The decoder comprises a source of positive and negative reference voltages; a differential input operational amplifier having its non-inverting input connected to ground; a storage capacitor CO=16Co connected as a feedback capacitor between the inverting input and the output terminals of the amplifier so that they operate as a voltage source; binary weighted capacitors C1=Co, C2=2Co, C3=4Co and C4=8Co; and a second unit weighted capacitor C5=Co. In an a-law decoder, switch means alternately connects one and other sides of ones of C1-C5 (1) between ground and either a.+-.reference voltage or ground, in accordance with characterizations in a PCM coded digital input word for sampling charge, and (2) between one side of CO and ground for transferring charge to CO for the first segment associated with a PCM word, and across CO for redistributing charge on the capacitors for other segments of a designated polarity. In a mu-law decoder, the switch means alternately connects one and other sides of ones of C1-C5 (1) between ground and either a.+-.reference voltage or ground, in accordance with the characterizations in a PCM coded digital input word, and (2) across the storage capacitor CO for redistributing charge on the capacitors for each segment of a designated polarity. The resultant analog signal established on CO in the eighth segment is sampled prior to resetting the charge voltage on CO to substantially zero volts and receipt of the next PCM input word.