The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 1984
Filed:
Nov. 06, 1981
Toshiya Takahashi, Tokyo, JP;
Yoshikuni Sato, Tokyo, JP;
Nippon Electric Co., Ltd., Tokyo, JP;
Abstract
A data processing system including a central processing unit (CPU), a memory device operating on a data word length of 2 m-bits, an input/output device operating on a data word length of m bits, an m-bit register and a direct memory access (DMA) controller for transferring data words in both directions between the memory device and the input/output device independently of the CPU. A 2 m-bit bus is connected between the memory device and two m-bit buses connected to a bus switching circuit which controls the transfer of m-bit data words between the 2 m-bit bus and the register and the input/output device. A control circuit generates timing and switching signals such that, during a first bus cycle a first m-bit data word from the input/ouput device is stored in the register, and during a second bus cycle a second m-bit data word from the input/output device is transferred directly via the buses to the memory device and, also, the first m-bit data word, stored in the register, is transferred to the memory device. For transfer of a data word from the memory device to the input/output device, during a first bus cycle m bits of data are transferred directly via the buses to the input/output device and, also, the following m bits are stored in the register, and during a second bus cycle the following m bits are transferred to the input/output device.