Method for fabricating mos device with self-aligned contacts

Abstract

A method for fabricating an integrated circuit semiconductor device comprised of an array of MOSFET elements having self-aligned or self-registered connections with conductive interconnect lines. The method involves the formation on a substrate of a thick oxide insulation layer (30) surrounding openings (99) therein for the MOSFET elements. A gate electrode (38) within each opening is utilized to provide self-registered source (42) and drain (44) regions and is covered on all sides and on its top surface with a gate dielectric layer (46). After the formation of the source-drain regions a relatively thin dielectric protective layer (38) is applied to the entire chip prior to the application of an upper insulative layer (50). When oversized windows are etched in the upper insulative layer, the protective layer prevents etching of the gate dielectric layer (46), thus preventing shorts or leaks between conductive and active areas and providing self-aligned contacts with minimum spacing from adjacent conductive areas (40). With the present method, additional internal protection over prior art devices is provided in MOS devices with source-drain regions formed either by diffusion or ion implantation.