Method of fabricating a monolithic integrated circuit structure

Abstract

Method of fabricating a monolithic integrated circuit structure incorporating complementary metal-oxide-silicon field effect transistors (CMOS FET's) including providing a body of silicon produced by conventional techniques having a sector of N-type and a sector of P-type each covered by a thin silicon oxide layer and a thin silicon nitride layer. The regions of the body adjacent to each of the sectors are covered by a thicker silicon oxide field layer. Portions of the thin nitride and oxide layers are removed to expose spaced apart zones in each of the sectors. Adherent contact members of low resistivity polycrystalline silicon of N and P-type conductivity are formed in contact with the exposed surfaces of the zone in the P and N-type sectors, respectively. Where N and P-type contact members are contiguous a rectifying junction is produced. The surfaces of the polycrystalline contact members are metallized with a highly conductive material, thereby shorting out the rectifying junctions. P-type conductivity imparting material is implanted through a gate oxide layer into the N-type sector except the portion shielded by a first gate electrode and the contact members. N-type conductivity imparting material is implanted through a gate oxide layer into the P-type sector except the portions shielded by a second gate electrode and the contact members. The body is heated to drive the implanted conductivity type imparting materials further into the sectors and to diffuse conductivity type imparting material from the contact members into the adjacent zones.