Mos power-on reset circuit

Abstract

A MOS power-on reset circuit includes Schmitt trigger circuit and an inverter. The Schmitt trigger circuit comprises first, second, and third depletion transistors serially connected between reference potential and supply voltage. The first and second depletion transistors are connected at a first junction point, and the second and third depletion transistors are connected at a second junction point. The gates of the first and second depletion transistors are commonly connected for receiving an input substrate bias voltage. An enhancement transistor is connected between the first junction point and supply voltage. The gates of the enhancement transistor and the third depletion transistor are commonly connected to the second junction point, which is the output of the Schmitt trigger circuit and which is coupled to the inverter from which the output voltage is taken. The transfer characteristic of the circuit exhibits hysteresis, with two trigger levels of input substrate bias voltage that differ sufficiently in magnitude that a triggering at one level, accompanied by a fluctuation in input voltage, will not cause a spurious triggering at the other level. Undesired oscillation of the circuit is thereby avoided.