Memory tester having memory repair analysis under pattern generator

Abstract

A memory tester is disclosed for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix under address control of a programmable pattern generator to derive failure data and stores the failure data in corresponding rows and columns in a second memory matrix. Failure data in the second memory is scanned by an error analysis circuit, under control of the pattern generator, first by row and when the number of failures in any row exceed the number of spare columns that row is flagged for replacement. Next, the columns of failure data are scanned and when the number of failures in any column exceeds the number of spare rows, that column is flagged for replacement. During the scan of the columns, previously flagged rows are masked such that failures which are to be repaired are not counted. Thereafter, with the flagged rows and column failures masked, the rows are again scanned and individual failures are flagged for replacement by remaining spare rows and columns until all spare rows and columns are used at which point detection of a subsequent failure flags the memory under test as non-repairable. This repairability analysis is performed in accordance with instructions stored in a memory of the error analysis circuit and called up under control of the pattern generator.