The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 1984

Filed:

Apr. 03, 1981
Applicant:
Inventors:

Haruyasu Yamada, Hirakata, JP;

Toyoki Takemoto, Yahata, JP;

Tadao Komeda, Ikoma, JP;

Tsutomu Fujita, Hirakata, JP;

Yuichi Hirofuji, Hirakata, JP;

Hiroyuki Sakai, Moriguchi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307459 ; 307477 ;
Abstract

In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.


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