Circuit for checking memory cells of programmable mos-integrated

Abstract

Circuit arrangement for checking memory cells of programmable MOS-integrated semiconductor memories, especially non-volatile semiconductor memories of the floating-gate type, has an active programming and read mode of operation wherein all word lines of the semiconductor memory with the exception of one selected word line are at a low level. The circuit arrangement also has an inactive power-down mode of operation, wherein all word lines at a high level. Both of the modes of operation are represented by a signal having a first level for the active mode of operation and a second level for the inactive mode of operation. The circuit arrangement further includes a single circuit in the semiconductor memory switchable via a first signal indicating the operating mode for the memory cell test, wherein all of the word lines are addressed by a voltage corresponding to the programming voltage, as a function of a single second signal fed into the semiconductor memory from the outside, from the level indicating the active mode of operation to the level indicating the inactive mode of operation, so that all the word lines can be switched simultaneously to the level required for programming.