The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 1984

Filed:

Mar. 01, 1982
Applicant:
Inventor:

James L Vorhaus, Newton, MA (US);

Assignee:

Raytheon Company, Lexington, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01P / ;
U.S. Cl.
CPC ...
333164 ; 333161 ; 333246 ;
Abstract

A phase shifter includes three cascade interconnected phase shift stages. Each stage includes a quadrature coupler and a pair of field effect transistors (FET), having a pair of gates, a drain, and a source, connected in a common (grounded) source configuration. The drain of each FET is coupled to an input port of the quadrature coupler to provide two signal paths having an electrical pathlength difference corresponding to a 90.degree. differential phase shift. In the third stage, a length of transmission line is coupled between a drain of one of the FET's and one input port of the coupler to provide a signal path having an electrical pathlength corresponding to a 180.degree. phase shift. An input signal is fed to one of the gates of each FET of the first stage, and voltage level control signals are fed to the second one of gates of each FET of the first stage, to control the amplitude of the signal coupled to each drain. The phase shift of the input signal at the output of the quadrature coupler is selected by controlling the ratio of the amplitudes of the signals coupled to each drain. The phase shift of the input signal through succeeding stages is selected in response to a second set of control signals fed to the second gates of each FET which select the signal paths through each stage.


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