The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 1984
Filed:
Sep. 01, 1982
Hans Kriedt, Munich, DE;
Andreas Dietze, Valley, DE;
Siemens Aktiengesellschaft, Berlin and Munich, DE;
Abstract
Integrable signal-processing semiconductor circuit, including four transistors being combined into two pairs, the transistors of each pair being connected together through their current inputs forming first and second differential amplifiers, the current outputs of one transistor of each transistor pair being connected to each other and to a first signal output and the current outputs of the other transistor pair being connected to each other and to a second signal output, third and fourth differential amplifiers addressed by first and second signals, first and second current mirror amplifiers each being connected to one output of the third differential amplifier, third and fourth current mirror amplifiers each being connected to one output of the fourth differential amplifier, reference potential connected to the current mirror amplifiers, a supply potential connected to the current outputs of the transistors, two load elements connected to the supply potential, the current inputs of the transistors of the first differential being connected to the first current mirror amplifier and the current inputs of the transistors of the second differential amplifier being connected to the second current mirror amplifier, the controls of one transistor of each pair being connected together to the third current mirror amplifier and through one load element to the supply potential, and the controls electrode of the other transistor of each pair being connected together to the fourth current mirror amplifier and through the other load element to the supply potential.