The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 1984

Filed:

Dec. 01, 1981
Applicant:
Inventors:

Robin F Farrow, Malvern, GB;

Gordon R Jones, Malvern, GB;

Philip W Sullivan, Malvern, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 2315 ; 357-4 ; 357 237 ;
Abstract

An FET device comprises a substrate with source and drain regions separated by a gate structure. Between the gate and substrate is an insulator formed of a cubic fluorite structure material that is lattice matched within 1% to the substrate. The insulator may be a group II fluoride such as Ca.sub.y Cd.sub.1-y F.sub.2 (0.ltoreq.y.ltoreq.1), Sr.sub.z Ba.sub.1-z F.sub.2 (0.ltoreq.z.ltoreq.1), or Ba.sub.x Ca.sub.1-x F.sub.2 (0.ltoreq.x.ltoreq.1), or an oxide such as CeO.sub.2, PbO.sub.2. The substrate may be a bulk semiconductor or an epitaxial layer such as Si, InP, GaAs, Ga.sub.x Al.sub.1-x As, GaSb, InAs, or AlAs.


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