The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 1984
Filed:
May. 12, 1980
Paul W Casper, Melbourne, FL (US);
Norman C Seiler, West Melbourne, FL (US);
Thomas J Nixon, Gaithersburg, MD (US);
George A Waschka, Jr, Melbourne, FL (US);
Charles R Patisaul, Melbourne, FL (US);
James W Toy, Melbourne, FL (US);
Willie T Burton, Jr, Palm Bay, FL (US);
W B Ashley, Manhattan Beach, CA (US);
Fred J Orlando, Jr, West Melbourne, FL (US);
Ronald R Giri, Melbourne, FL (US);
Peter H Halpern, Longwood, FL (US);
J Richard Jones, Melbourne, FL (US);
Harold Iley, Huntsville, AL (US);
Harris Corporation, Melbourne, FL (US);
Abstract
A repeatered, multichannel fiber optic communication network includes a plurality of full duplex fiber optic channels and one or more auxiliary channels. In order to supervise and control the operation of the network, for both data transmission and fault/maintenance actions, each terminal station contains a processor-based subsystem capable of network monitoring, first level maintenance action, fault isolation, and remote network control and status reporting. This processor-based subsystem interfaces with each fiber optic channel, with an orderwire communication link, and with external input/output devices and surveillance equipment. Three substantially autonomous processor-based sections which are dedicated to performing specific functions within the overall network operation are employed for carrying out these separate interfacing tasks. Each section of the processor-based subsystem in a terminal station contains its own CPU and associated memory and is programmed to carry out specific functions identified with that section. Each section is interconnected with the other two so that, internally, the subsystem is fully integrated.