Cycle stealing i/o controller with programmable offline mode of operation

Abstract

A dual mode microprocessor acts either as a front-end IO controller processor relative to a primary host processor and device or as a secondary data processor having independent storage, processing and IO capabilities. Host software prepares a list of device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor so as to evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a programmable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, performing this transfer in an autonomous manner, i.e., without assistance from either processor. In PO mode the microprocessor directs associated elements to perform one or more programs of operations defined by secondary commands contained in a command list which is transferred to the microprocessor's memory by special PO mode 'LOAD' type DCB's, and interpreted in response to special PO mode type 'START' DCB's. A list transferred by one LOAD DCB may be repeatedly accessed at various positions by several START DCB's. The architecture of the command list includes commands which permit the microprocessor to exchange data with the host and/or a device, perform arithmetic operations on data, perform bit and byte manipulative operations on data, and directly control the device interface.