The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 1984

Filed:

Sep. 07, 1983
Applicant:
Inventor:

Peter S Gwozdz, Cupertino, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
C23F / ; B44C / ; C03C / ; C03C / ;
U.S. Cl.
CPC ...
156643 ; 29591 ; 156644 ; 156646 ; 156653 ; 156656 ; 156657 ; 1566591 ; 2041 / ; 357 71 ; 427 90 ; 430317 ; 430318 ;
Abstract

A method for forming multiple conductive interconnect layers on a semiconductor device comprises defining a first conductive metal layer, applying a first insulating layer thereon, planarizing the first insulating layer by etching a sacrificial planarization layer, applying a second insulating layer, forming vias through first and second insulating layers and applying a second conductive layer thereon. Optionally, a third insulating layer can be applied over the first two and stepped vias formed to improve the interconnection of the first and second layers. The method reduces metallization failure associated with irregularities in the intermediate insulating layers.


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