The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 1984

Filed:

Aug. 17, 1981
Applicant:
Inventors:

Jean-Pierre Petit, 22220 Treguier, FR;

Xavier Maitre, 22300 Lannion, FR;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364724 ;
Abstract

Digital processing circuit forming a weighted sum of digital signals. It comprises n groups of M series registers (10/1, . . . , 10/nM) into which are introduced the signals to be processed, n multiplexers (15/1, 15/2, . . . , 15/n), a memory (20) containing precalculated quantities characteristic of the weighted sum to be formed, said memory having a capacity of 2 .sup..beta.+n words distributed into different blocks, a modulo M counter (25), an adder-subtracter (30) connected to the memory, an accumulator-register (40) connected to the adder-subtracter and a clock (50) actuating the counter and the registers. The circuit is in that the memory is subdivided into [M-(2.sup..beta. -M)] blocks of 2.sup.n words and into (2.sup..beta. -M) blocks of 2.sup.n+1 words, said blocks being selected by the bits supplied to the outputs of the counter, in that it comprises supplementary series registers, whose number is at the most equal to 2.sup..beta. -M, said series registers receiving the supplementary signals to be processed and in that it also comprises a multplexing means (21) controlled by the outputs of the counter.


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