The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 1984

Filed:

Dec. 08, 1982
Applicant:
Inventors:

Henricus G Maas, Eindhoven, NL;

Johannes A Appels, Eindhoven, NL;

Assignee:

U.S. Philips Corporation, New York, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
29580 ; 29571 ; 156653 ; 156648 ;
Abstract

According to the invention, at least one oxidation-preventing layer (2) is provided on the substrate region (1), while on this layer there is provided an oxidizable layer (3). The oxidizable layer (3) is removed above part of the substrate region (1). An edge portion (5) of the oxidizable layer (3) is oxidized. Subsequently, at least the uncovered part of the oxidation-preventing layer (2) is removed selectively and the exposed part of the substrate region is thermally oxidized through part of its thickness, while practically only at the area of the oxidized edge portion (5) the substrate region (1) is exposed and is etched away through at least part of its thickness in order to form a groove (8), the oxidizable layer (3) and the oxidized edge portion (5) being removed completely. The substrate region may be a mono- or polycrystalline silicon layer. The oxidizable layer may consist of for instance polycrystalline silicon and may be coated with a second oxidation-preventing layer (4). If the substrate region is a masking layer, the slots provided therein may be used for doping purposes, for example, for forming channel stoppers, etc. Application in particular for the manufacture of integrated circuits and of gate electrodes spaced apart by very small distances in IGFET and CCD structures. FIG. 9 is suitable for abridgment.


Find Patent Forward Citations

Maas, Henricus. (1984). Method of providing a narrow groove or slot in a substrate region, in (U.S. Patent No. 4449287). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4449287

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