The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 1984

Filed:

Nov. 02, 1981
Applicant:
Inventors:

Volkmar Goetze, Grafenau, DE;

Ekkehard F Miersch, Boeblingen, DE;

Guenther Potz, Sindelfingen, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365182 ; 365189 ; 357 23 ;
Abstract

For read-only storages and in particular for PLA applications, improved coupling elements together with an associated personalization scheme permit the storing of at least two memory (or logic) connection patterns selectable independently of each other. Quick electrical switching between at least two functional modes in the same storage array, is also provided. One device field effect transistor (FET) cells with specific gate configurations depending on the respective personalization state are used as coupling elements. For instance, in a two-fold personalization permanent storage, the coupling elements consist of FETs with two gate sections provided one beside the other. For a connection to be established in only one of the two possible functions at the respective crosspoint, one of the gate sections is connected to the control line provided for the functional selection. The remaining gate section is connected to the associated input line. A connection in the other functional mode is provided correspondingly with only the control lines being switched. If at the respective crosspoint a connection is to be effective in both functional modes, both gate sections are jointly connected to the respective input line. By using only one common peripheral circuit, PLAs with multiple personalization properties can be made in integrated technology, with the same semiconductor area requirement as PLAs personalizable into only one functional mode.


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