The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 1984
Filed:
Jun. 16, 1981
Mark W Mueller, Cedar Park, TX (US);
Thomas S Parker, Cedar Park, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A communication adapter circuit (10) is connected to a processor through processor I/O interface buses (12, 14). Data and control signals are provided through the buses (12, 14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a modem interface bus (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA RS 232 interface circuit (60) to a conventional modem or through a bus (64) to an internal modem. A phase locked loop (PLL) circuit in the control circuit (24) generates a data clock signal on a line (33) for operation of the adapter circuit (10) in the bisynchronous protocol with a non-clock-generating modem.