The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 1984
Filed:
Mar. 25, 1982
Jeffrey R Fox, Concord, MA (US);
GTE Laboratories Incorporated, Waltham, MA (US);
Abstract
An MOS FET inverter driver circuit. A first FET of the depletion type, a resistance formed by a depletion type FET having its gate connected to its drain, and a second FET of the enhancement type are connected in series between a positive voltage source and ground. Third and fourth FET's both of the enhancement type are also connected in series between the voltage source and ground. The gates of the first, second, and fourth FET's are connected directly to an input terminal. The gate of the third FET is connected to the juncture of the resistance FET and the second FET. A capacitance is connected between the juncture of the resistance FET and the first FET and the juncture of the third and fourth FET's, an output terminal is also connected to this juncture. The circuit obtains bootstrap action by virtue of the capacitance to provide high voltage drive to turn the third FET, the output pull-up transistor, on. The direct connection from the input terminal to the gates of the first, second, and fourth FET's further contributes to high speed operation of the circuit.