The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 1984

Filed:

Jun. 17, 1982
Applicant:
Inventor:

Michael F Wicnienski, Antioch, IL (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307597 ; 307593 ; 307603 ; 307470 ; 307311 ; 328 73 ;
Abstract

A circuit is provided for resetting a digital logic circuit, such as a digital counter. A switch 16 provides a first signal when a predetermined condition has occcurred. A flip-flop 24 provides an output reset signal when the flip-flop is in a first state, in response to the first signal. The digital logic circuit to be reset 32 is coupled to the output of the flip-flop 24 for receiving its output reset signal. Feedback means 34, 36, 38 are coupled from the digital logic circuit 32 back to the flip-flop 24 for providing a signal to put the flip-flop into its other state whereby its output reset signal is terminated.


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Wicnienski, Michael. (1984). Level sensitive reset circuit for digital logic (U.S. Patent No. 4438357). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4438357

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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