Hysteresis circuit having a stable output free from noise superposed on

Abstract

A hysteresis circuit has first and second input terminals and an output terminal. An input signal is supplied to the first input terminal, while the second input terminal receives a reference voltage. Control electrodes of first and second transistors are connected to the first and second input terminals. The two transistors are interconnected to form a differential amplifier having an output which is supplied to a phase-inversion amplifier. The output of the phase-inversion amplifier is fed to the output terminal. The load impedances of both the first and second transistors are varied depending upon the output condition of the output terminal. For example, when the output terminal is in one output condition, a third transistor is turned on and a fourth transistor is turned off. When the output terminal is in an opposite output condition, the conduction conditions of the third and fourth transistors are reversed. In other words, each time that the voltage level at the output terminal is inverted, the load impedance of both the first and second transistors are varied, to change the gain of the differential amplifier. This gain variation is fed back to reinforce the output condition.