The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 1984

Filed:

Aug. 06, 1981
Applicant:
Inventors:

Burkhard Giebel, Munich, DE;

Hans Moormann, Haar, DE;

Lothar Schrader, Munich, DE;

Assignee:

Siemens Aktiengesellschaft, Berlin & Munich, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365203 ; 365104 ; 365206 ;
Abstract

Circuit arrangement for a read-only memory organized in rows and columns, including bit lines having potentials applied thereto, and selection circuits being connected to the bit lines, being addressed by a bit line decoder and containing at least one selection transistor having a cut-off voltage and a gate potential, for preventing bit line potentials from dropping below a given value at which the selection circuits become conducting without having been selected by the bit line decoder, including current-feed lines each being connected to a different one of the bit lines for feeding current to the bit lines and for ensuring that for each of the selection circuits not selected by the bit line decoder the difference between at least one gate potential of the participating selection transistors and the respective bit line potential is smaller than the cut-off voltage of the respective selection transistors.


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