Atrial-based, atrial-ventricular sequential cardiac pacer

Abstract

Atrial refractory and ventricular inhibit functions are independently implemented in an atrial-synchronized pacer. Spontaneous signals on the ventricular lead inhibit ventricular stimulation for a predetermined interval independent of the atria, except when there is noise on the ventricular lead. The atrial-based pacing logic establishes the usual refractory period following spontaneous P-waves, and when noise is detected on the atrial lead, the pacing logic reverts to a fixed atrial rate. The ventricular-inhibited logic includes a retriggerable noise timing circuit and a non-retriggerable inhibit timing circuit both triggered by the output of the ventricular sense amplifier. The output of the inhibit circuit disables the ventricular stimulation output circuit. However, if the output of the noise circuit stays high for an interval indicative of electromagnetic interference, the trigger input to the inhibit timing circuit is disabled to permit ventricular stimulation. Meanwhile, the pacing logic institutes fixed rate pacing due to atrial noise. In AV synchronous and atrial-synchronized AV sequential pacer embodiments, the digital pacing logic uses existing circuitry while the ventricular-inhibited logic is implemented by an add-on RC-timed circuit. In the AV sequential pacer, the AV delay circuit is separate from the pacing logic, and its input is provided by the atrial sense amplifier normally and by the output of the pacing logic during ventricular noise.