Demultiplexer circuit

Abstract

A demultiplexer circuit which extracts from an incoming time division multiplexed digital bit stream any combination of PCM encoded words or data bits, irrespective of the rate of latter or the position of the data bits in a given channel or channels. The demultiplexer circuit includes a random access memory (12) for storing information as to the bit(s) to be demultiplexed out of the incoming digital bit stream. A counter (13) operates in synchronism with the received bit stream and the output thereof serves to access the random access memory to provide output signals indicative of the bit(s) carrying information for the subscriber station. These output signals are utilized to read the digital signals intended for said station into other random access memory (31, 41). A summing circuit (16-19) is coupled to the input of said other memory so that conference calls are summed in real time. The digital signals are then read out of the other memory at a steady rate, with a stored data signal being similarly outputted irrespective of the rate of the signal or its position in a given channel or channels.