Clock pulse phase shifter

Abstract

As shown in FIG. 8, a phase shifter for phase shifting a single frequency clock signal CK as produced by an oscillator (813) comprises an inverter (805) and a delay network (804) for producing phase quadrature versions I.sub.ac, I.sub.ac and Q.sub.ac, Q.sub.ac of the signal. A current generator (803) produces control currents I.sub.c, I.sub.c and Q.sub.c, Q.sub.c, the magnitudes of which are determined by a control voltage V.sub.c whose magnitude represents a required phase shift. Two multipliers (801) and (802) multiply the signal pairs I.sub.ac, I.sub.ac and I.sub.c, I.sub.c ; and the signal pairs Q.sub.ac, Q.sub.ac and Q.sub.c, Q.sub.c, to produce resultant quadrature signals which are combined in an adder (806) to produce the phase shifted clock signal CLK (and CLK). The phase shift range is made to cover a number of cycles by an arrangement comprising two limit detectors (807) and (808), an OR-gate ( 809), a .div.2 circuit (810), and two reversing switches (811) and (812). This arrangement serves to reverse the sense of the control voltage V.sub.c at each limit of its operating range so that this range can be used successively a number of times to represent progressive phase shift. The current generator (803) can also be modified to provide control currents representing a phase shift of more than one cycle.