Demultiplexer circuit

Abstract

A demultiplexer circuit which extracts from an incoming time division multiplexed digital bit stream any combination of PCM encoded words (in separate channels), or data bits irrespective of the rate of the latter or the position of the data bits in a given channel. The demultiplexer circuit includes a random access memory (12) (RAM) for storing information as to the channel(s) to be demultiplexed out of the incoming digital bit stream. A counter (13) operates in synchronism with the received bit stream and the output thereof serves to access the RAM to provide output signals indicative of the channel(s) carrying information for the subscriber station. These output signals are utilized to read the digital signals intended for said station into a shift register (16). A summing circuit (17, 18) is interconnected with the register so that conference calls are summed in real time. Before the next frame of digital signals, the contents of the register are transferred to a second shift register (21). The digital signals are then read out of the second register at a steady rate, with a stored data signal being similarly outputted irrespective of the rate of the same or its position in a given channel.