The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 1984
Filed:
Sep. 16, 1980
Akira Matsunaga, Hitachi, JP;
Keiichi Morita, Hitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A glass-moulded type semiconductor device comprising semiconductor arrangement composed of at least one semiconductor pellet having at least one P-N junction, edges of which are exposed to peripheral surfaces of the semiconductor pellet, a pair of electrodes secured to opposite ends of the semiconductor arrangement through a brazing material, a first mould glass layer secured to the entire circumferential surface of the semiconductor arrangement and extending to the surfaces of the electrodes for passivating the P-N junction of the semiconductor arrangement, and a second mould glass in the form of at least one layer secured to the surface of said first mould glass layer. Thermal expansion coefficient of each of the mould glass layers is selected in such a manner that the thermal expansion coefficient of the first glass layer is larger than the apparent thermal expansion coefficient of a semiconductor assembly consisting of the semiconductor arrangement and the brazing material, and the thermal expansion coefficient of said second mould glass layer is larger than that of the first mould glass layer.