The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 1984

Filed:

Jun. 26, 1981
Applicant:
Inventor:

Katusuke Furuya, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G07D / ;
U.S. Cl.
CPC ...
377-7 ; 377 39 ; 133 / ; 371 67 ;
Abstract

An electrical circuit arrangement for use in a coin counting device is provided. The arrangement is provided with an abnormality detection circuit for generating an alarm signal when any of the optical sensing member of the coin counting device is hindered from operating normally due to adhesion of dust or other causes. The abnormality detection circuit includes a NAND gate, a NOR gate, an OR gate, a counter and an SR-type flip-flop. The first and second detection signal generated from the optical sensing members are supplied to the NAND gate and the NOR gate. The OR gate is supplied with the output from the NOR gate and a reset signal from a reset operator section. The counter is supplied with the output from the NAND gate and the output from the OR gate. In normal operation, the counter counts the level '1' and '0' of the binary logical level alternately, thereby to leave a counting section to continue the counting operation. If any abnormality occurs at any of the combined optical sensing members, the number counted by said counter takes the value 2, whereupon a second output signal indicating the occurrence of abnormality is generated by the counter and fed to the flip-flop which generates an alarm signal.


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